When a complimentary metal oxide semiconductor (CMOS) circuit is in a quiescent state, ideally no current is drawn from the power source by the circuit. A defective CMOS logic device may tend to draw current from the power source. In theory, it is possible to characterize a CMOS logic device by measuring the quiescent drain (source) current IDDQ and find such a defective device. Although a defective CMOS device may exhibit abnormal behavior in its transient current, it is generally anticipated that the abnormal transient current due to a defective individual gate will be masked by the overall circuit transient current. Of course it is possible to build a current detector for almost every logic gate so that an abnormal transient current can become detectable and the test speed improved. However, such an approach would require much overhead and is probably impractical in application.
There is much information regarding various prior art quiescent current testing methods, including : "A Built-In Current Monitor for CMOS VLSI Circuits", by A. Rubio, et al., published by IEEE in 1995 at the European Design and Test Conference held in Paris, France; "Built-in Current Testing, by W. Maly and M. Patyra, published in the IEEE Journal of Solid State Circuits, Vol. 27, No. 3, Mar. 1992; "Proportional BIC Sensor for Current Testing" by J. Rius and J. Figueras, published in Journal of Electronic Testing, Theory and Applications, 1992; and "Built-In Current Sensor for IDDQ Test in CMOS" by C. Hsue and C. Lin, published by AT&T Bell Laboratories in Princeton, NJ, from the International Test Conference 1993.
As seen in the prior art, quiescent current testing is efficient in CMOS digital circuits, offering high coverage levels for detecting significant defects and requiring only a reduced number of test vectors. On-chip built-in current sensors have some advantages over the off-chip alternatives, as on-chip sensors are able to detect defective quiescent current levels with more discrimination and at relatively higher test speeds. The design of reliable circuits has become a key point in the application of current testing techniques. Quiescent current testing circuits have been evaluated for use in testing very large scale integrated (VLSI) CMOS circuits. A significant set of sensor developments are available.
The current of a static CMOS cell is not constant through time. When an output clock transition occurs, a peak of IDD current is observed. This peak is due to the charging and discharging of the load capacitance at the output circuit nodes and additionally to the overlap current through the PMOS and NMOS transistors in the circuit portion changing state. When the transition is completed, the cell is in the quiescence state and, in practice, IDD is near to zero and remains in this range until a new transition occurs. The quiescent current is very sensitive to circuit degradation and other defects which generate IDDQ many orders of magnitude greater than the normal IDDQ. This characteristic is applied to detect defects by use of IDDQ current.
Basically the measurement of the defective current of a device is obtained through observation of the degraded level of the device Vdd. This is due to the discharge of the parasitic capacitance of the power supply line of the device, Vdd. Referring to FIG. 2, IDDQ current measurements require an additional Vdd pad or a pseudo Vdd (PVdd) to supply dynamic current through a switch, illustrated in FIG. 2 as switch 20. Two external digital signals, activation 12 and monitor 14 are used to determine a delay time indicative of a defective current. Note that the circuit labeled monitor label 10 in FIG. 2 may be repeated for every Vdd pin on the chip.
Quiescent current measurements and tests offer information regarding many aspects of the CMOS device. It is desirable to streamline device testing and specifically the quiescent current testing by reducing the hardware associated with the testing as well as reducing the time required for such tests. It is also desirable to expand quiesent testing and so reduce the number of tests required to guarantee fault coverage.